Design and Performance Evaluation of an Optimized Signed Booth Multiplier Using Verilog HDL

Abstract

The multiplication of signed integers is a fundamental arithmetic operation widely used in embedded systems, digital signal processing, and machine learning accelerators. This paper presents the design, synthesis, and FPGA implementation of an optimized signed Booth multiplier using Verilog Hardware Description Language (HDL). The proposed design employs the Booth algorithm to reduce the number of partial products through efficient encoding of the multiplier, followed by addition, subtraction, and arithmetic shift operations, thereby lowering hardware complexity while maintaining computational accuracy. To strengthen implementation validity, the design was functionally verified using simulation tools and further synthesized using Synopsys Design Compiler to evaluate timing performance and optimization capability. Timing analysis confirmed successful closure with a positive slack of 0.05 ns under a 5 ns clock period, indicating that all timing constraints were satisfied without violations. The Booth Multiplier was successfully designed and implemented using Verilog HDL in Quartus II, achieving a maximum operating frequency of 245.82 MHz, demonstrating efficient hardware performance on the target device. Timing analysis using Synopsys Design Compiler with a 5 ns period confirms timing closure with a positive slack of 0.05 ns under the specified operating conditions. In terms of hardware utilization, the design occupied only 21 Adaptive Logic Modules (ALMs) out of 56,480 available resources and used 27 registers, highlighting its compact resource footprint. The proposed Booth multiplier demonstrates competitive timing performance with efficient area utilization. These results confirm that the developed architecture provides a reliable and resource-efficient solution for signed integer multiplication, making it suitable for high-speed real-time digital systems and FPGA-based arithmetic accelerators.